The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process technology. Its low sleep current, 30 mA ... The ...
see the entire Source and Sink Current 100mA LDO for 28nm cascade I/O, UMC 28nm HPC Logic and Mixed-Mode Process datasheet get in contact with Source and Sink Current 100mA LDO for 28nm cascade I/O, ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback